Following on from the previous page on the CPU and Von Neumann Architecture, we’re going to look at how the CPU carries out these instructions using the fetch-decode-execute cycle…
- Copy the memory address from the program counter to the MAR.
- Copy the instruction stored in the MAR address to the MDR.
- Increment (increase) the program counter to point to the address of the next instruction, ready for the next cycle.
- The instruction in the MDR is decoded by the CU.
- The CU may then prepare for the next step, e.g. by loading values into the MAR or MDR.
- The instruction is performed.
- This could be: loading data from memory, writing data to memory, doing a calculation or logic operation (using the ALU), changing the address in the PC, or stopping the program.