Fetch-Decode-Execute Cycle

Following on from the previous page on the CPU and Von Neumann Architecture, we’re going to look at how the CPU carries out these instructions using the fetch-decode-execute cycle…

Fetch-Decode-Execute Cycle



  1. Copy the memory address from the program counter to the MAR.
  2. Copy the instruction stored in the MAR address to the MDR.
  3. Increment (increase) the program counter to point to the address of the next instruction, ready for the next cycle.


  1. The instruction in the MDR is decoded by the CU.
  2. The CU may then prepare for the next step, e.g. by loading values into the MAR or MDR.


  1. The instruction is performed.
  2. This could be: loading data from memory, writing data to memory, doing a calculation or logic operation (using the ALU), changing the address in the PC, or stopping the program.